Algorithms for routing and testing routability of planar VLSI layouts
STOC '85 Proceedings of the seventeenth annual ACM symposium on Theory of computing
Routability of a rubber-band sketch
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Generating sparse partial inductance matrices with guaranteed stability
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Pin assignment and routing on a single-layer Pin Grid Array
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Interchangeable pin routing with application to package layout
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
SPIE: sparse partial inductance extraction
DAC '97 Proceedings of the 34th annual Design Automation Conference
DAC '98 Proceedings of the 35th annual Design Automation Conference
Digital systems engineering
Inductance 101: analysis and design issues
Proceedings of the 38th annual Design Automation Conference
How to efficiently capture on-chip inductance effects: introducing a new circuit element K
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
I/O Pad Assignment Based on the Circuit Structure
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Intrinsic Area Array ICs: What, Why, and How?
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
I/O Cell Placement and Electrical Checking Methodology for ASICs with Peripheral I/Os
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Effects of Package Stackups on Microprocessor Performance
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Implications of Area-Array I/O for Row-Based Placement Methodology
IPDI '98 Proceedings of the IEEE Symposium on IC/Package Design Integration
A global routing method for 2-layer ball grid array packages
Proceedings of the 2005 international symposium on Physical design
Simultaneous escape routing and layer assignment for dense PCBs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Constraint driven I/O planning and placement for chip-package co-design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A routing algorithm for flip-chip design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An escape routing framework for dense boards with high-speed design constraints
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Optimal routing algorithms for pin clusters in high-density multichip modules
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Power-centric design of high-speed I/Os
Proceedings of the 43rd annual Design Automation Conference
Efficient escape routing for hexagonal array of high density I/Os
Proceedings of the 43rd annual Design Automation Conference
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Layer minimization of escape routing in area array packaging
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
An integer linear programming based routing algorithm for flip-chip design
Proceedings of the 44th annual Design Automation Conference
Off-chip decoupling capacitor allocation for chip package co-design
Proceedings of the 44th annual Design Automation Conference
Topological routing to maximize routability for package substrate
Proceedings of the 45th annual Design Automation Conference
An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Risks for Signal Integrity in System in Package and Possible Remedies
ETS '08 Proceedings of the 2008 13th European Test Symposium
Stochastic current prediction enabled frequency actuator for runtime resonance noise reduction
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Communication Systems
A correct network flow model for escape routing
Proceedings of the 46th Annual Design Automation Conference
Resistive and inductive skin effect in rectangular conductors
IBM Journal of Research and Development
EMPIRE: an efficient and compact multiple-parameterized model-order reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling and design for beyond-the-die power integrity
Proceedings of the International Conference on Computer-Aided Design
A faster algorithm for rubber-band equivalent transformation for planar VLSI layouts
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Return-limited inductances: a practical approach to on-chip inductance extraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
I/O placement for FPGAs with multiple I/O standards
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient In-Package Decoupling Capacitor Optimization for I/O Power Integrity
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The unquenched thirst for higher levels of electronic systems integration and higher performance goals has produced a plethora of design and business challenges that are threatening the success enjoyed so far as modeled by Moore's law. To tackle these challenges and meet the design needs of consumer electronics products such as those of cell phones, audio/video players, digital cameras that are composed of a number of different technologies, vertical system integration has emerged as a required technology to reduce the system board space and height in addition to the overall time-to-market and design cost. System-in-package (SiP) is a system integration technology that achieves the aforementioned needs in a scalable and cost-effective way, where multiple dies, passive components, and discrete devices are assembled, often vertically, in a package. This paper surveys the electrical and layout perspectives of SiP. It first introduces package technologies, and then presents SiP design flow and design exploration. Finally, the paper discusses details of beyond-die signal and power integrity and physical implementation such as I/O (input/output cell) placement and routing for redistribution layer, escape, and substrate.