Adaptive filter theory (2nd ed.)
Adaptive filter theory (2nd ed.)
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
SRAM Test Using On-Chip Dynamic Power Supply Current Sensor
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
Built-In Dynamic Current Sensor for Hard-to-Detect Faults in Mixed-Signal Ics
Proceedings of the conference on Design, automation and test in Europe
Incremental partitioning-based vectorless power grid verification
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming
Proceedings of the 43rd annual Design Automation Conference
Understanding voltage variations in chip multiprocessors using a distributed power-delivery network
Proceedings of the conference on Design, automation and test in Europe
Efficient decoupling capacitance budgeting considering operation and process variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Optimal decoupling capacitor sizing and placement for standard-cell layout designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Runtime resonance noise reduction with current prediction enabled frequency actuator
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling and design for beyond-the-die power integrity
Proceedings of the International Conference on Computer-Aided Design
System-in-Package: Electrical and Layout Perspectives
Foundations and Trends in Electronic Design Automation
| Hi-index | 0.00 |
Power delivery network (PDN) is a distributed RLC network with its dominant resonance frequency in the low-to-middle frequency range. Though high-performance chips' working frequencies are much higher than this resonance frequency in general, chip runtime loading frequency is not. When a chip executes a chunk of instructions repeatedly, the induced current load may have harmonic components close to this resonance frequency, causing excessive power integrity degradation. Existing PDN design solutions are, however, mainly targeted at reducing high-frequency noise and not effective to suppress such resonance noise. In this work, we propose a novel approach to proactively suppress this type of noise. A method based on a high dimension generalized Markov process is developed to predict current load variation. Based on such prediction, a clock frequency actuator design is proposed to proactively select an optimal clock frequency to suppress the resonance. To the best of our knowledge, this is the first in-depth study on proactively reducing runtime instruction execution induced PDN resonance noise.