Intrinsic Area Array ICs: What, Why, and How?
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
Constraint driven I/O planning and placement for chip-package co-design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Proceedings of the 2006 international symposium on Physical design
Noise driven in-package decoupling capacitor optimization for power integrity
Proceedings of the 2006 international symposium on Physical design
Off-chip decoupling capacitor allocation for chip package co-design
Proceedings of the 44th annual Design Automation Conference
Stochastic current prediction enabled frequency actuator for runtime resonance noise reduction
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Simultaneous switching noise analysis using application specific device modeling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-in-Package: Electrical and Layout Perspectives
Foundations and Trends in Electronic Design Automation
A silicon-validated methodology for power delivery modeling and simulation
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
Power integrity gains growing importance for integrated circuits in 45nm technology and beyond. This paper provides a tutorial of modeling and design for beyond the die power integrity. We explain the background of simultaneous switching noise (SSN) and its impacts on circuit designs. We discuss various models of different accuracy and complexity for the board, package and chip, and suggest how to select proper ones for board-package-chip co-simulation and co-design of SSN. We then review different design techniques to suppress SSN, including I/O planning and placement, decoupling capacitor allocation, package layer stacking and power/ground plane stapling.