I/O Pad Assignment Based on the Circuit Structure
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Design Implementation of Intrinsic Area Array ICs
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
CAD Tools for Area-Distributed I/O Pad Packaging
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
Intrinsic Area Array ICs: What, Why, and How?
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
Implications of Area-Array I/O for Row-Based Placement Methodology
IPDI '98 Proceedings of the IEEE Symposium on IC/Package Design Integration
A Clustering Based Area I/O Planning for Flip-Chip Technology
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Proceedings of the 2004 international symposium on Physical design
Engineering details of a stable force-directed placer
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Simultaneous escape routing and layer assignment for dense PCBs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
I/O placement for FPGAs with multiple I/O standards
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
URBAN CRIME ANALYSIS THROUGH AREAL CATEGORIZED MULTIVARIATE ASSOCIATIONS MINING
Applied Artificial Intelligence
Signal skew aware floorplanning and bumper signal assignment technique for flip-chip
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Diffusion-driven congestion reduction for substrate topological routing
Proceedings of the 2009 international symposium on Physical design
Fast flip-chip pin-out designation respin for package-board codesign
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Effective congestion reduction for IC package substrate routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Row-based area-array I/O design planning in concurrent chip-package design flow
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Modeling and design for beyond-the-die power integrity
Proceedings of the International Conference on Computer-Aided Design
System-in-Package: Electrical and Layout Perspectives
Foundations and Trends in Electronic Design Automation
A chip-package-board co-design methodology
Proceedings of the 49th Annual Design Automation Conference
A study of row-based area-array I/O design planning in concurrent chip-package design flow
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multiple chip planning for chip-interposer codesign
Proceedings of the 50th Annual Design Automation Conference
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System-on-chip and system-in-package result in increased number of I/O cells and complicated constraints for both chip designs and package designs. This renders the traditional manually tuned and chip-centered I/O designs suboptimal in terms of both turn around time and design quality. In this paper we formally introduce a set of design constraints suitable for chip-package co-design. We formulate a constraint-driven I/O planning and placement problem, and solve it by a multi-step algorithm based upon integer linear programming. Experiment results using real industry designs show that the proposed algorithm can effectively find a large scale I/O placement solution and satisfy all given design constraints in less than 10 minutes. In contrast, the state-of-the-art without considering those design constraints simply cannot meet all design constraints by relying solely upon the conventional iterative approach.