Design of FPGAs with area I/O for field programmable MCM
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Signal integrity optimization on the pad assignment for high-speed VLSI design
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Mongrel: hybrid techniques for standard cell placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Force directed mongrel with physical net constraints
Proceedings of the 40th annual Design Automation Conference
Design Implementation of Intrinsic Area Array ICs
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Area I/O Flip-Chip Packaging to Minimize Interconnect Length
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
CAD Tools for Area-Distributed I/O Pad Packaging
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
I/O Cell Placement and Electrical Checking Methodology for ASICs with Peripheral I/Os
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Implications of Area-Array I/O for Row-Based Placement Methodology
IPDI '98 Proceedings of the IEEE Symposium on IC/Package Design Integration
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Constraint driven I/O planning and placement for chip-package co-design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Reporting of standard cell placement results
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Signal skew aware floorplanning and bumper signal assignment technique for flip-chip
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Row-based area-array I/O design planning in concurrent chip-package design flow
Proceedings of the 16th Asia and South Pacific Design Automation Conference
A study of row-based area-array I/O design planning in concurrent chip-package design flow
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Due to higher input/output (I/O) count and power delivery problem in deep submicrometer (DSM) regime, flip-chip technology, especially for area-array architecture, has provided more opportunities for adoption than traditional peripheral bonding design style in high-performance application-specific integrated circuit and microprocessor designs. However, it is hard to tell which technique can provide better design cost edge in usually concerned perspectives. In this paper, we present a methodology to convert a previous peripheral bonding design to an area-I/O flip-chip design. It is based on an I/O buffer modeling and an I/O planning algorithm to legalize I/O buffer blocks with core placement without sacrificing much of the previous optimization in the original core placement. The experimental results have shown that we have achieved better area and I/O wirelength in area-IO flip-chip configuration (especially for pad-limit designs), compared with peripheral bonding configuration in packaging consideration.