Design of FPGAs with area I/O for field programmable MCM
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Design Implementation of Intrinsic Area Array ICs
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
A Clustering Based Area I/O Planning for Flip-Chip Technology
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Constraint driven I/O planning and placement for chip-package co-design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
The importance of adopting a package-aware chip design flow
Proceedings of the 43rd annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Novel pin assignment algorithms for components with very high pin counts
Proceedings of the conference on Design, automation and test in Europe
Area-I/O flip-chip routing for chip-package co-design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
An integer-linear-programming-based routing algorithm for flip-chip designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast flip-chip pin-out designation respin for package-board codesign
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A chip-package-board co-design methodology
Proceedings of the 49th Annual Design Automation Conference
Multiple chip planning for chip-interposer codesign
Proceedings of the 50th Annual Design Automation Conference
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IC-centric design flow has been a common paradigm when designing and optimizing a system. Package and board/system designs are usually followed by almost-ready chip designs, which causes long turn-around time communicating with package and system houses. In this paper, the realizations of area-array I/O design methodologies are studied. Different from IC-centric flow, we propose a chip-package concurrent design flow to speed up the design time. Along with the flow, we design the I/O-bump (and P/G-bump) tile which combines I/O (and P/G) and bump into a hard macro with the considerations of I/O power connection and electrostatic discharge (ESD) protection. We then employ an I/O-row based scheme to place I/O-bump tiles with existed metal layers. By such a scheme, it reduces efforts in I/O placement legalization and the redistribution layer (RDL) routing. With the emphasis on package design awareness, the proposed methods map package balls onto chip I/Os, thus providing an opportunity to design chip and package in parallel. Due to this early study of I/O and bump planning, faster convergence can be expected with concurrent design flow. The results are encouraging and the merits of this flow are reassuring.