Single-layer fanout routing and routability analysis for Ball Grid Arrays
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Constraint driven I/O planning and placement for chip-package co-design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Row-based area-array I/O design planning in concurrent chip-package design flow
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Efficient package pin-out planning with system interconnects optimization for package-board codesign
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A chip-package-board co-design methodology
Proceedings of the 49th Annual Design Automation Conference
Multiple chip planning for chip-interposer codesign
Proceedings of the 50th Annual Design Automation Conference
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Deep submicrometer effects drive the complication in designing chips, as well as in package designs and communications between package and board. As a result, the iterative interface design has been a time-consuming process. This paper proposes a novel and efficient approach to designating pin-out, which is a package ball chart describing pin locations for flip-chip BGA package when designing chipsets. The proposed approach can not only automate the assignment of more than 200 input/output (I/O) pins on package, but also precisely evaluate package size which accommodates all pins with almost no void pin positions, as good as the one from manual design. Furthermore, the practical experience and techniques in designing such interface has been accounted for, including signal integrity, power delivery and routability. This efficient pin-out designation and package size estimation by pin-block design and floorplanning provides much faster turn around time, thus enormous improvement in meeting design schedule. Our pin-block design contains two major parts. First, we have pin-block construction to locate signal pins within a block along the specific patterns. Six pin patterns are proposed as templates which are automatically generated according to the user-defined constraints. Second, we have pin-blocks grouping to group all pin-blocks into package boundaries. Two alternative pin-blocks grouping strategies are provided for various applications such as chipset and field-programmable gate array (FPGA). The results on two real cases show that our methodology is effective in achieving almost the same dimensions in package size, compared with manual design in weeks, while simultaneously considering critical issues and package size migration in package-board codesign.