Constraint driven I/O planning and placement for chip-package co-design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Simultaneous block and I/O buffer floorplanning for flip-chip design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Routing for chip-package-board co-design considering differential pairs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Area-I/O flip-chip routing for chip-package co-design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Introduction to Algorithms, Third Edition
Introduction to Algorithms, Third Edition
A correct network flow model for escape routing
Proceedings of the 46th Annual Design Automation Conference
Fast flip-chip pin-out designation respin for package-board codesign
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Area-I/O flip-chip routing for chip-package co-design considering signal skews
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Row-based area-array I/O design planning in concurrent chip-package design flow
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Board driven I/O planning & optimization
Proceedings of the International Conference on Computer-Aided Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multiple chip planning for chip-interposer codesign
Proceedings of the 50th Annual Design Automation Conference
| Hi-index | 0.00 |
In today's IC production, the design processes of chips, packages, and boards are typically separate from each other. The lack of information from other domains causes significant design convergence problems and greatly reduces design quality. In this paper, we propose the first chip-package-board code-sign methodology that provides true bi-directional information interactions among the three design domains. The code-sign adopts a two-pass flow of board-package-chip followed by chip-package-board routing interactions to facilitate the overall design integration. Experimental results show that our code-sign flow succeeds in the routing for all test cases, while a traditional flow and two board-driven flows fail all cases.