Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
TCG: a transitive closure graph-based representation for non-slicing floorplans
Proceedings of the 38th annual Design Automation Conference
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Multilevel floorplanning/placement for large-scale modules using B*-trees
Proceedings of the 40th annual Design Automation Conference
Implementation and extensibility of an analytic placer
Proceedings of the 2004 international symposium on Physical design
Proceedings of the 2004 international symposium on Physical design
An area-optimality study of floorplanning
Proceedings of the 2004 international symposium on Physical design
Recursive bisection based mixed block placement
Proceedings of the 2004 international symposium on Physical design
Fractional Cut: Improved Recursive Bisection Placement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
ACG-Adjacent Constraint Graph for General Floorplans
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Are floorplan representations important in digital design?
Proceedings of the 2005 international symposium on Physical design
Multilevel generalized force-directed method for circuit placement
Proceedings of the 2005 international symposium on Physical design
Multi-level placement for large-scale mixed-size IC designs
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Area-I/O flip-chip routing for chip-package co-design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Signal skew aware floorplanning and bumper signal assignment technique for flip-chip
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Area-I/O flip-chip routing for chip-package co-design considering signal skews
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A chip-package-board co-design methodology
Proceedings of the 49th Annual Design Automation Conference
Multiple chip planning for chip-interposer codesign
Proceedings of the 50th Annual Design Automation Conference
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The flip-chip package gives the highest chip density of any packaging method to support the pad-limited ASIC design. One of the most important characteristics of flip-chip designs is that the input/output buffers could be placed anywhere inside a chip. In this paper, we first introduce the floorplanning problem for the flip-chip design and formulate it as assigning the positions of input/output buffers and first-stage/last-stage blocks so that the path length between blocks and bump balls as well as the delay skew of the paths are simultaneously minimized. We then present a hierarchical method to solve the problem. We first cluster a block and its corresponding buffers to reduce the problem size. Then, we go into iterations of the alternating and interacting global optimization step and the partitioning step. The global optimization step places blocks based on simulated annealing using the B*-tree representation to minimize a given cost function. The partitioning step dissects the chip into two subregions, and the blocks are divided into two groups and are placed in respective subregions. The two steps repeat until each subregion contains at most a given number of blocks, defined by the ratio of the total block area to the chip area. At last, we refine the floorplan by perturbing blocks inside a subregion as well as in different subregions. Compared with the B*-tree based floorplanner alone, our method is more efficient and obtains significantly better results, with an average cost of only 51.8% of that obtained by using the B*-tree alone, based on a set of real industrial flip-chip designs provided by leading companies.