A global routing method for 2-layer ball grid array packages
Proceedings of the 2005 international symposium on Physical design
Simultaneous block and I/O buffer floorplanning for flip-chip design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An integer linear programming based routing algorithm for flip-chip design
Proceedings of the 44th annual Design Automation Conference
A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A correct network flow model for escape routing
Proceedings of the 46th Annual Design Automation Conference
Flip-chip routing with unified area-I/O pad assignments for package-board co-design
Proceedings of the 46th Annual Design Automation Conference
An efficient pre-assignment routing algorithm for flip-chip designs
Proceedings of the 2009 International Conference on Computer-Aided Design
Area-I/O flip-chip routing for chip-package co-design considering signal skews
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ILP-based inter-die routing for 3D ICs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Row-based area-array I/O design planning in concurrent chip-package design flow
Proceedings of the 16th Asia and South Pacific Design Automation Conference
IO connection assignment and RDL routing for flip-chip designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Recent research development in PCB layout
Proceedings of the International Conference on Computer-Aided Design
Recent research development in flip-chip routing
Proceedings of the International Conference on Computer-Aided Design
On the escape routing of differential pairs
Proceedings of the International Conference on Computer-Aided Design
A chip-package-board co-design methodology
Proceedings of the 49th Annual Design Automation Conference
Thermo-mechanical analysis of TSV and solder interconnects for different Cu pillar bump types
Microelectronic Engineering
A study of row-based area-array I/O design planning in concurrent chip-package design flow
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Escape routing of mixed-pattern signals based on staggered-pin-array PCBs
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Multiple chip planning for chip-interposer codesign
Proceedings of the 50th Annual Design Automation Conference
On effective flip-chip routing via pseudo single redistribution layer
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
The area-I/O flip-chip package provides a high chip-density solution to the demand of more I/O's in VLSI designs; it can achieve smaller package size, shorter wirelength, and better signal and power integrity. In this paper, we introduce the routing problem for chip and package co-design and present the first work in the literature to handle the multiple Re-Distribution Layer (RDL) routing problem for flip-chip designs, considering pin and layer assignment, total wirelength minimization, and chip-package co-design. Our router adopts a two-stage technique of global routing followed by RDL routing. The global routing assigns each block port to a unique bump pad via an I/O pad and decides the RDL routing among I/O pads and bump pads. Based on the minimum-cost maximum-flow algorithm, we can guarantee 100% RDL routing completion after the assignment and the optimal solution with the minimum wirelength. The RDL routing efficiently distributes the routing points between two adjacent bump pads and then generates a 100% routable sequence to complete the routing. Experimental results based on 10 industry designs demonstrate that our router can achieve 100% routability and the optimal routing wirelength under reasonable CPU times, while related works cannot.