Area-I/O flip-chip routing for chip-package co-design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Signal skew aware floorplanning and bumper signal assignment technique for flip-chip
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A correct network flow model for escape routing
Proceedings of the 46th Annual Design Automation Conference
An integer-linear-programming-based routing algorithm for flip-chip designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient pre-assignment routing algorithm for flip-chip designs
Proceedings of the 2009 International Conference on Computer-Aided Design
Area-I/O flip-chip routing for chip-package co-design considering signal skews
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Global routing and track assignment for flip-chip designs
Proceedings of the 47th Design Automation Conference
An optimal algorithm for finding disjoint rectangles and its application to PCB routing
Proceedings of the 47th Design Automation Conference
ILP-based inter-die routing for 3D ICs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Row-based area-array I/O design planning in concurrent chip-package design flow
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Escape routing for staggered-pin-array PCBs
Proceedings of the International Conference on Computer-Aided Design
Recent research development in PCB layout
Proceedings of the International Conference on Computer-Aided Design
Recent research development in flip-chip routing
Proceedings of the International Conference on Computer-Aided Design
On the escape routing of differential pairs
Proceedings of the International Conference on Computer-Aided Design
Obstacle-avoiding free-assignment routing for flip-chip designs
Proceedings of the 49th Annual Design Automation Conference
A study of row-based area-array I/O design planning in concurrent chip-package design flow
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Escape routing of mixed-pattern signals based on staggered-pin-array PCBs
Proceedings of the 2013 ACM international symposium on International symposium on physical design
On effective flip-chip routing via pseudo single redistribution layer
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.03 |
The flip-chip package gives the highest chip density of any packaging method to support the pad-limited application-specific integrated circuit designs. In this paper, we propose the first router for the flip-chip package in the literature. The router can redistribute nets from wire-bonding pads to bump pads and then route each of them. The router adopts a two-stage technique of global routing followed by detailed routing. In global routing, we use the network flow algorithm to solve the assignment problem from the wire-bonding pads to the bump pads and then create the global path for each net. The detailed routing consists of three stages, namely: 1) cross-point assignment; 2) net ordering determination; and 3) track assignment, to complete the routing. Experimental results based on seven real designs from the industry demonstrate that the router can reduce the total wirelength by 10.2%, the critical wirelength by 13.4%, and the signal skews by 13.9%, as compared with a heuristic algorithm currently used in industry.