Single-layer wire routing and compaction
Single-layer wire routing and compaction
Network flows: theory, algorithms, and applications
Network flows: theory, algorithms, and applications
Interchangeable pin routing with application to package layout
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
SURF: Rubber-Band Routing System for Multichip Modules
IEEE Design & Test
A Faster Algorithm for Finding Disjoint Paths in Grids
ISAAC '99 Proceedings of the 10th International Symposium on Algorithms and Computation
INTERCHANGEABLE PIN ROUTING WITH APPLICATION TO PACKAGE LAYOUT
INTERCHANGEABLE PIN ROUTING WITH APPLICATION TO PACKAGE LAYOUT
Layer minimization of escape routing in area array packaging
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A correct network flow model for escape routing
Proceedings of the 46th Annual Design Automation Conference
An integer-linear-programming-based routing algorithm for flip-chip designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Area-I/O flip-chip routing for chip-package co-design considering signal skews
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Global routing and track assignment for flip-chip designs
Proceedings of the 47th Design Automation Conference
An optimal algorithm for layer assignment of bus escape routing on PCBs
Proceedings of the 48th Design Automation Conference
A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The flip-chip packaging is introduced for modern IC designs with higher integration density and larger I/O counts. It is necessary to consider routing obstacles for modern flip-chip designs, where the obstacles could be regions blocked for signal integrity protection (especially for analog/mixed-signal modules), pre-routed or power/ground nets, and even for through-silicon vias for 3D IC designs. However, no existing published works consider obstacles. To remedy this insufficiency, this paper presents the first work to solve the free-assignment flip-chip routing problem considering obstacles. For the free-assignment routing problem, most existing works apply the network-flow formulation. Nevertheless, we observe that no existing network-flow model can exactly capture the routability of a local routing region (tile) in presence of obstacles. This paper presents the first work that can precisely model the routability of a tile, even with obstacles. Based on this new model, a two-stage approach of global routing followed by detailed routing is proposed. The global routing computes a routing topology by the minimum-cost maximum-flow algorithm, and the detailed routing determines the precise wire positions. Dynamic programming is applied to further merge tiles to reduce the problem size. Compared to a state-of-the-art flow model with obstacle handling extensions, experimental results show that our algorithm can achieve 100% routability for all circuits while the extensions of the previous work cannot complete routing for any benchmark circuit with obstacles.