Data structures and network algorithms
Data structures and network algorithms
Computational geometry: an introduction
Computational geometry: an introduction
Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
Single-layer wire routing and compaction
Single-layer wire routing and compaction
Routability of a rubber-band sketch
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Pin assignment and routing on a single-layer Pin Grid Array
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
Single-layer fanout routing and routability analysis for Ball Grid Arrays
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
SURF: Rubber-Band Routing System for Multichip Modules
IEEE Design & Test
An Optimum Pin Redistribution for Multichip Modules
MCMC '96 Proceedings of the 1996 IEEE Multi-Chip Module Conference (MCMC '96)
INTERCHANGEABLE PIN ROUTING WITH APPLICATION TO PACKAGE LAYOUT
INTERCHANGEABLE PIN ROUTING WITH APPLICATION TO PACKAGE LAYOUT
Efficient breakout routing in printed circuit boards
SCG '97 Proceedings of the thirteenth annual symposium on Computational geometry
Yield-preferred via insertion based on novel geotopological technology
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A routing algorithm for flip-chip design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Topological routing to maximize routability for package substrate
Proceedings of the 45th annual Design Automation Conference
Diffusion-driven congestion reduction for substrate topological routing
Proceedings of the 2009 international symposium on Physical design
Octilinear redistributive routing in bump arrays
Proceedings of the 19th ACM Great Lakes symposium on VLSI
A correct network flow model for escape routing
Proceedings of the 46th Annual Design Automation Conference
Flip-chip routing with unified area-I/O pad assignments for package-board co-design
Proceedings of the 46th Annual Design Automation Conference
Substrate topological routing for high-density packages
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Effective congestion reduction for IC package substrate routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Escape routing for staggered-pin-array PCBs
Proceedings of the International Conference on Computer-Aided Design
Recent research development in PCB layout
Proceedings of the International Conference on Computer-Aided Design
On the escape routing of differential pairs
Proceedings of the International Conference on Computer-Aided Design
System-in-Package: Electrical and Layout Perspectives
Foundations and Trends in Electronic Design Automation
Obstacle-avoiding free-assignment routing for flip-chip designs
Proceedings of the 49th Annual Design Automation Conference
Escape routing of mixed-pattern signals based on staggered-pin-array PCBs
Proceedings of the 2013 ACM international symposium on International symposium on physical design
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Many practical routing problems such as BGA, PGA, pin redistribution and test fixture routing involve routing with interchangeable pins. These routing problems, especially package layout, are becoming more difficult to do manually due to increasing speed and I/O. Currently, no commercial or university router is available for this task. In this paper, we unify these different problems as instances of the interchangeable pin routing (IPR) problem, which is NP-complete. By representing the solution space with flows in a triangulated routing network instead of grids, we developed a min-cost max-flow heuristic considering only the most important cuts in the design. The heuristic handles multiple layers, prerouted nets, and all-angle, octilinear or rectilinear wiring styles. Experiments show that the heuristic is very effective on most practical examples. It had been used to route industry designs with thousands of interchangeable pins.