Interchangeable pin routing with application to package layout
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
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Abstract: We introduce an optimum algorithm for the pin redistribution problem which arises in Multi-Chip Modules. The problem is to redistribute the pins in chip layer to the pin redistribution layers, using a minimum number of layers. The proposed algorithm is based on a two-stage approach, global routing followed by layer assignment. Each subproblem has an optimality structure. Based on min-cost flow formulation along with graph manipulations, we propose a performance-driven algorithm to minimize the number of layers and also simultaneously optimize the wirelength and the number of bends.