Single-layer fanout routing and routability analysis for Ball Grid Arrays
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Interchangeable pin routing with application to package layout
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Efficient escape routing for hexagonal array of high density I/Os
Proceedings of the 43rd annual Design Automation Conference
Layer minimization of escape routing in area array packaging
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Routing for chip-package-board co-design considering differential pairs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Area-I/O flip-chip routing for chip-package co-design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A correct network flow model for escape routing
Proceedings of the 46th Annual Design Automation Conference
Escape routing for staggered-pin-array PCBs
Proceedings of the International Conference on Computer-Aided Design
Recent research development in PCB layout
Proceedings of the International Conference on Computer-Aided Design
On the escape routing of differential pairs
Proceedings of the International Conference on Computer-Aided Design
A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Escape routing has become a critical issue in high-speed PCB routing. Most of previous work paid attention to either differential-pair escape routing or single-signal escape routing but few considered them together. In this paper, a unified ILP model is used to formulate the problem of escape routing of differential pairs together with single signals (mixed-pattern signals) on staggered pin array. A mixed-pattern escape routing algorithm is proposed to solve the problem and a slice-based heuristic method is presented to speed up the algorithm. Experimental results show that the proposed method is very efficient. It can solve all the test cases in short time and improve wire length and chip area by 13.8% and 13.4% respectively compared to traditional pin array. At the same time, the method can increase routability by 16.3% and reduce the wire length by 9.3% compared to a two-stage method.