Single-layer fanout routing and routability analysis for Ball Grid Arrays
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Escaping a grid by edge-disjoint paths
SODA '00 Proceedings of the eleventh annual ACM-SIAM symposium on Discrete algorithms
Octilinear redistributive routing in bump arrays
Proceedings of the 19th ACM Great Lakes symposium on VLSI
A correct network flow model for escape routing
Proceedings of the 46th Annual Design Automation Conference
Substrate topological routing for high-density packages
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
B-escape: a simultaneous escape routing algorithm based on boundary routing
Proceedings of the 19th international symposium on Physical design
Effective congestion reduction for IC package substrate routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An optimal algorithm for finding disjoint rectangles and its application to PCB routing
Proceedings of the 47th Design Automation Conference
Escape routing for staggered-pin-array PCBs
Proceedings of the International Conference on Computer-Aided Design
Recent research development in PCB layout
Proceedings of the International Conference on Computer-Aided Design
On the escape routing of differential pairs
Proceedings of the International Conference on Computer-Aided Design
System-in-Package: Electrical and Layout Perspectives
Foundations and Trends in Electronic Design Automation
Obstacle-avoiding free-assignment routing for flip-chip designs
Proceedings of the 49th Annual Design Automation Conference
Escape routing of mixed-pattern signals based on staggered-pin-array PCBs
Proceedings of the 2013 ACM international symposium on International symposium on physical design
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We devise a central triangular sequence to minimize the escape routing layers in area array packaging. We use a network flow model to analyze the bottleneck of the routable pins. The triangular patterns are generated in a reverse order from the last to the first layer. We demonstrate that the triangular pin sequence maximizes the sum of escape pins in the accumulated layers and thus minimize the number of escape routing layers. A test case is presented to illustrate the approach.