Substrate topological routing for high-density packages

Authors:
Shenghua Liu;Guoqiang Chen;Tom Tong Jing;Lei He;Tianpei Zhang;Robi Dutta;Xian-Long Hong
Affiliations:
Department of Computer Science and Technology, Tsinghua University, Beijing, China;Magma Design Automation, Inc., San Jose, CA;Synopsys, Inc., Mountain View, CA and Department of Electrical Engineering, University of California, Los Angeles, Los Angeles, CA;Department of Electrical Engineering, UCLA, Los Angeles, CA;Cadence Design Systems, San Jose, CA and University of Minnesota, Minneapolis, MN;Magma Design Automation, Inc., San Jose, CA;Department of Computer Science and Technology, Tsinghua University, Beijing, China
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2009

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Abstract

Off-chip substrate routing for high-density packages is on the critical path for time to market. Compared with on-chip routers, existing commercial tools for off-chip routing have lower routability and often result in a large number of unrouted nets for manual routing. In this paper, we explain why planar routing is still required with multiple routing layers for substrate routing and then propose a flexible via-staggering technique to improve routability. In addition, we develop an efficient yet effective substrate routing algorithm, applying dynamic pushing to tackle the net ordering problem and reordering and rerouting to further reduce wire length and congestion. Compared with an industrial design tool that leaves 936 nets unrouted for nine industrial designs with a total of 6100 nets, our algorithm reduces the unrouted nets to 212, a 4.5-times net number reduction, which translates to design time reduction.