Introduction to algorithms
On the complexity of approximating the independent set problem
Information and Computation
Placement and routing tools for the Triptych FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An algorithm for simultaneous pin assignment and routing
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Pin assignment in automated printed circuit board design
DAC '72 Proceedings of the 9th Design Automation Workshop
Length-Matching Routing for High-Speed Printed Circuit Boards
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Constraint driven I/O planning and placement for chip-package co-design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An escape routing framework for dense boards with high-speed design constraints
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Optimal bus sequencing for escape routing in dense PCBs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Substrate topological routing for high-density packages
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
B-escape: a simultaneous escape routing algorithm based on boundary routing
Proceedings of the 19th international symposium on Physical design
Effective congestion reduction for IC package substrate routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
New optimal layer assignment for bus-oriented escape routing
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Recent research development in PCB layout
Proceedings of the International Conference on Computer-Aided Design
System-in-Package: Electrical and Layout Perspectives
Foundations and Trends in Electronic Design Automation
New optimal layer assignment for bus-oriented escape routing
Integration, the VLSI Journal
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As die sizes are shrinking, and circuit complexities are increasing, the PCB routing problem becomes more and more challenging. Traditional routing algorithms can not handle these challenges effectively, and many high-end designs in the industry require manual routing efforts. In this paper, we propose a problem decomposition that distinguishes routing within dense components from routing in the intermediate area. In particular, we propose an effective methodology to find the escape routing solution for multiple components simultaneously such that the number of crossings in the intermediate area is minimized. For this, we model the problem as a longest path with forbidden pairs (LPFP) problem, and propose two algorithms for it. The first is an exact polynomial-time algorithm that is guaranteed to find the maximal planar routing solution on one layer. The second is a randomized algorithm that has good scalability characteristics for large circuits. Then we use these algorithms to assign the maximal subset of planar nets to each layer, and then distribute the remaining nets at the end. We demonstrate the effectiveness of these algorithms through experiments on industrial circuits.