A global routing method for 2-layer ball grid array packages
Proceedings of the 2005 international symposium on Physical design
Monotonic parallel and orthogonal routing for single-layer ball grid array packages
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A routing algorithm for flip-chip design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Topological routing to maximize routability for package substrate
Proceedings of the 45th annual Design Automation Conference
Diffusion-driven congestion reduction for substrate topological routing
Proceedings of the 2009 international symposium on Physical design
Substrate topological routing for high-density packages
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An integer-linear-programming-based routing algorithm for flip-chip designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Effective congestion reduction for IC package substrate routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Given a die with I/O pads wire bonded onto the multilayer substrates of a pin grid array (PGA) package, a three-step net-even-wiring system (NEWS) is proposed to complete the routing of the bond pads to the corresponding grid pins on one or more layers. First, we performed a maximum-cut partitioning on a net interference graph for the layer assignment step. Second, nets on each layer were converted to planar sketches using a novel insertion sort method. Last, the planar sketches were transformed into a net-even-wired layout using a simplified rubber-band router