Single-layer fanout routing and routability analysis for Ball Grid Arrays
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An Even Wiring Approach to the Ball Grid Array Package Routing
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
A Via Assignment and Global Routing Method for 2-Layer Ball Grid Array Packages
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
NEWS: a net-even-wiring system for the routing on a multilayer PGA package
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Monotonic parallel and orthogonal routing for single-layer ball grid array packages
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A routing algorithm for flip-chip design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An integer linear programming based routing algorithm for flip-chip design
Proceedings of the 44th annual Design Automation Conference
Topological routing to maximize routability for package substrate
Proceedings of the 45th annual Design Automation Conference
Novel pin assignment algorithms for components with very high pin counts
Proceedings of the conference on Design, automation and test in Europe
Routing for chip-package-board co-design considering differential pairs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Area-I/O flip-chip routing for chip-package co-design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Signal skew aware floorplanning and bumper signal assignment technique for flip-chip
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Diffusion-driven congestion reduction for substrate topological routing
Proceedings of the 2009 international symposium on Physical design
A correct network flow model for escape routing
Proceedings of the 46th Annual Design Automation Conference
Substrate topological routing for high-density packages
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An integer-linear-programming-based routing algorithm for flip-chip designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Effective congestion reduction for IC package substrate routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Area-I/O flip-chip routing for chip-package co-design considering signal skews
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Recent research development in PCB layout
Proceedings of the International Conference on Computer-Aided Design
On the escape routing of differential pairs
Proceedings of the International Conference on Computer-Aided Design
System-in-Package: Electrical and Layout Perspectives
Foundations and Trends in Electronic Design Automation
A study of row-based area-array I/O design planning in concurrent chip-package design flow
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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In current VLSI circuits, there can be hundreds of required I/O pins. BGA(Ball Grid Array) packaging is commonly used to realize the huge number of connections between VLSI and PCB. In this paper, we propose a global routing method for two-layer BGA packages. In our routing model, the global routing for each net is uniquely determined by a via assignment. Our global routing method begins with an initial feasible via assignment and incrementally improves the via assignment to minimize the total wire length and wire congestion. In each iteration, a via assignment is improved by exchanging adjacent two vias, rotating three vias, or by moving vias to their adjacent grids one by one. Our method is a greedy-based heuristic. The algorithm efficiently generates better global routes than initial routes with respect to wire congestion and total wire length.