Efficient algorithms for finding maximum matching in graphs
ACM Computing Surveys (CSUR)
An optimal channel pin assignment with multiple intervals for building block layout
EURO-DAC '92 Proceedings of the conference on European design automation
Pin assignment and routing on a single-layer Pin Grid Array
ASP-DAC '95 Proceedings of the 1995 Asia and South Pacific Design Automation Conference
An Efficient Implementation of Edmonds' Algorithm for Maximum Matching on Graphs
Journal of the ACM (JACM)
An approach to pin assignment in printed circuit board design
ACM SIGDA Newsletter
I/O Pad Assignment Based on the Circuit Structure
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Pin assignment on a printed circuit board
DAC '78 Proceedings of the 15th Design Automation Conference
Pin assignment in automated printed circuit board design
DAC '72 Proceedings of the 9th Design Automation Workshop
A global routing method for 2-layer ball grid array packages
Proceedings of the 2005 international symposium on Physical design
Towards Integration of Quadratic Placement and Pin Assignment
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Pin assignment for multi-FPGA systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal simultaneous pin assignment and escape routing for dense PCBs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Row-based area-array I/O design planning in concurrent chip-package design flow
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Recent research development in PCB layout
Proceedings of the International Conference on Computer-Aided Design
Interface optimization for improved routability in chip-package-board co-design
Proceedings of the System Level Interconnect Prediction Workshop
A study of row-based area-array I/O design planning in concurrent chip-package design flow
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 0.00 |
The wiring effort and thus, the routability of electronic designs such as printed circuit boards, multi chip modules and single chip modules largely depends on the assignment of signals to component pins. For modern components that have as many as several thousand pins, this pin assignment cannot be optimized manually. This paper presents four novel pin assignment algorithms that automatically create optimized pin assignments for wiring substrate designs with components that have very high pin counts. We also present and evaluate quality estimation metrics that enable fast assessment of the pin assignment results. The efficiency of our algorithms allows the creation of optimized pin assignments using only minutes of computation time. We show the applicability of all four algorithms, including their strengths and weaknesses, in specific design applications.