A method of measuring nets routability for MCM's general area routing problems
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Estimating routing congestion using probabilistic analysis
Proceedings of the 2001 international symposium on Physical design
Accurate pseudo-constructive wirelength and congestion estimation
Proceedings of the 2003 international workshop on System-level interconnect prediction
Probabilistic congestion prediction
Proceedings of the 2004 international symposium on Physical design
Congestion prediction in early stages
Proceedings of the 2005 international workshop on System level interconnect prediction
Congestion prediction in floorplanning
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Prediction and reduction of routing congestion
Proceedings of the 2006 international symposium on Physical design
Probabilistic Congestion Prediction with Partial Blockages
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
The ISPD global routing benchmark suite
Proceedings of the 2008 international symposium on Physical design
Novel pin assignment algorithms for components with very high pin counts
Proceedings of the conference on Design, automation and test in Europe
Congestion prediction in early stages of physical design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Routing for chip-package-board co-design considering differential pairs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A correct network flow model for escape routing
Proceedings of the 46th Annual Design Automation Conference
Flip-chip routing with unified area-I/O pad assignments for package-board co-design
Proceedings of the 46th Annual Design Automation Conference
An integer-linear-programming-based routing algorithm for flip-chip designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal simultaneous pin assignment and escape routing for dense PCBs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Min-cost flow-based algorithm for simultaneous pin assignment and routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The simultaneous optimization of both pin assignment and pin routing for different hierarchy levels (chip, package, board) of an electronic system is a bottleneck in today's hierarchical co-design flows, typically requiring manual optimization strategies and multiple iterations. Specifically, a fast and finegrained evaluation of routability that considers all requirements between the different hierarchy levels is missing. In this paper we provide a comprehensive, fast method to evaluate the routability of interfaces in hierarchical systems based on a new probabilistic routability prediction. We implemented our methodology in an industrial design flow and achieved significant improvement in overall routing, including reduced manufacturing costs of chip-package-board co-designs.