Computational geometry: an introduction
Computational geometry: an introduction
Network flows: theory, algorithms, and applications
Network flows: theory, algorithms, and applications
Interchangeable pin routing with application to package layout
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
An integer linear programming based routing algorithm for flip-chip design
Proceedings of the 44th annual Design Automation Conference
Area-I/O flip-chip routing for chip-package co-design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Global routing and track assignment for flip-chip designs
Proceedings of the 47th Design Automation Conference
IO connection assignment and RDL routing for flip-chip designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Escape routing for staggered-pin-array PCBs
Proceedings of the International Conference on Computer-Aided Design
Recent research development in flip-chip routing
Proceedings of the International Conference on Computer-Aided Design
Interface optimization for improved routability in chip-package-board co-design
Proceedings of the System Level Interconnect Prediction Workshop
Multiple chip planning for chip-interposer codesign
Proceedings of the 50th Annual Design Automation Conference
On effective flip-chip routing via pseudo single redistribution layer
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper, we present a novel flip-chip routing algorithm for package-board co-design. Unlike the previous works that can consider only either free- or pre-assignment routing, our router is the first work in the literature that can handle both the free-and pre-assignment routing. Based on the computational geometry techniques (e.g., the Delaunay triangulation and the Voronoi diagram), the router applies a unified network-flow formulation to perform congestion estimation for the pre-assignment routing. According to the congestion map, the network-flow formulation can also consider the free-assignment nets during the routing for the pre-assignment ones. Then, the router modifies the network-flow formulation to optimally assign and route the free-assignment nets, considering the routed pre-assignment nets. With the package and board co-design flow, we can achieve 100% routing completion. Experimental results based on industry designs demonstrate the high-quality of our algorithm.