Computational geometry: algorithms and applications
Computational geometry: algorithms and applications
Introduction to Algorithms
General river routing algorithm
DAC '83 Proceedings of the 20th Design Automation Conference
Monotonic parallel and orthogonal routing for single-layer ball grid array packages
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A routing algorithm for flip-chip design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An integer linear programming based routing algorithm for flip-chip design
Proceedings of the 44th annual Design Automation Conference
Area-I/O flip-chip routing for chip-package co-design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
IO connection assignment and RDL routing for flip-chip designs
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
RDL pre-assignment routing for flip-chip designs
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Flip-chip routing with unified area-I/O pad assignments for package-board co-design
Proceedings of the 46th Annual Design Automation Conference
An efficient pre-assignment routing algorithm for flip-chip designs
Proceedings of the 2009 International Conference on Computer-Aided Design
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Given a set of IO buffers and a set of bump balls with the capacity constraints between two adjacent bump balls, based on the construction of the Delaunary triangulation and a Manhattan Voronoi diagram, an O(n2) assignment algorithm is proposed to assign all the IO connections in a single redistribution layer for IO connection assignment, where n is the number of bump balls in a flip-chip design. Furthermore, based on the computation of the probabilistic congestion for the assigned IO connections, an O(n2) routing algorithm is proposed to minimize the total wirelength to route all the assigned IO connections while satisfying the capacity constraints for single-layer RDL routing. Compared with the combination of a greedy IO assignment and our RDL routing, our IO assignment reduces the total wirelength by 9.9% and improves the routability by 8.8% on the average for 6 tested circuits. Compared with the combination of a greedy IO assignment, the single-layer BGA global router [Tomioka and Takahashi 2006] and our RDL detailed routing, our IO connection assignment and RDL routing reduces the total wirelength by 12.9% and improve the routability by 10.2% on the average for 6 tested circuits. Besides that the experimental results show that our IO connection assignment and RDL routing can reduce 52.1% of the total wirelength on the average to achieve 100% routability for 12 tested industrial circuits under reasonable CPU time.