An approach to pin assignment in printed circuit board design
ACM SIGDA Newsletter
SURF: Rubber-Band Routing System for Multichip Modules
IEEE Design & Test
Pin assignment on a printed circuit board
DAC '78 Proceedings of the 15th Design Automation Conference
Pin assignment in automated printed circuit board design
DAC '72 Proceedings of the 9th Design Automation Workshop
Length-Matching Routing for High-Speed Printed Circuit Boards
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Optimal bus sequencing for escape routing in dense PCBs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Novel pin assignment algorithms for components with very high pin counts
Proceedings of the conference on Design, automation and test in Europe
BSG-Route: a length-matching router for general topology
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A correct network flow model for escape routing
Proceedings of the 46th Annual Design Automation Conference
Recent research development in PCB layout
Proceedings of the International Conference on Computer-Aided Design
Interface optimization for improved routability in chip-package-board co-design
Proceedings of the System Level Interconnect Prediction Workshop
Hi-index | 0.00 |
In PCB designs, pin positions greatly affect routability of the design. State-of-the-art pin assignment algorithms are guided by simple (heuristic) metrics to estimate routability and thus have no guarantee to obtain a routable solution. In this paper, we present a novel approach to obtain a pin assignment solution that guarantees routability. We show that the problem of simultaneous pin assignment and escape routing can be solved optimally in polynomial time. We then focus on the pin assignment and escape routing for the terminals in a bus, and present algorithmic enhancements as well as discuss the trade-offs between single-layer and multi-layer implementations. We tested our approach on a state-of-the-art industrial board with 80 buses (over 7000 nets). The pin assignment and escape routing solutions for all the 80 buses are successfully obtainted in less than 5 minutes of CPU time.