Equidistance routing in high-speed VLSI layout design
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Untangling twisted nets for bus routing
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Algorithmic study of single-layer bus routing for high-speed boards
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Length-Matching Routing Algorithm for High-Performance Printed Circuit Boards
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact route matching algorithms for analog and mixed signal integrated circuits
Proceedings of the 2009 International Conference on Computer-Aided Design
Optimal layer assignment for escape routing of buses
Proceedings of the 2009 International Conference on Computer-Aided Design
BSG-route: a length-constrained routing scheme for general planar topology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Two-sided single-detour untangling for bus routing
Proceedings of the 47th Design Automation Conference
Optimal simultaneous pin assignment and escape routing for dense PCBs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Obstacle-aware longest path using rectangular pattern detouring in routing grids
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Obstacle-aware length-matching bus routing
Proceedings of the 2011 international symposium on Physical design
Recent research development in PCB layout
Proceedings of the International Conference on Computer-Aided Design
Maze routing algorithms with exact matching constraints for analog and mixed signal designs
Proceedings of the International Conference on Computer-Aided Design
Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits
Proceedings of the 50th Annual Design Automation Conference
| Hi-index | 0.00 |
Length-matching routing is a very important issue for PCB routing. Previous length-matching routers [1]--[3] all have assumptions on the routing topology whereas practical designs may be free of any topological constraint. In this paper, we propose a router that deals with general topology. Unlike previous routers, our router does not impose any restriction on the routing topology. Moreover, our router is gridless. Its performance does not depend on the routing grid size of the input while routers in [1]--[3] do. This is a big advantage because modern PCB routing configurations usually imply huge routing grids. The novelty of this work is that we view the length-matching routing problem as an area assignment problem and use a placement structure, Bounded-Sliceline Grid (BSG) [4], to help solving the problem. Experimental results show that our router can handle practical designs that previous routers can't handle. For designs that they could handle, our router runs much faster. For example, in one of our data, we obtain the result in 88 seconds while the router in [3] takes more than one day.