PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Equidistance routing in high-speed VLSI layout design
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Untangling twisted nets for bus routing
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
BSG-Route: a length-matching router for general topology
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Module packing based on the BSG-structure and IC layout applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Algorithmic study of single-layer bus routing for high-speed boards
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Length-Matching Routing Algorithm for High-Performance Printed Circuit Boards
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Recent research development in PCB layout
Proceedings of the International Conference on Computer-Aided Design
Post-route refinement for high-frequency PCBs considering meander segment alleviation
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Post-route alleviation of dense meander segments in high-performance printed circuit boards
Proceedings of the International Conference on Computer-Aided Design
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Length-constrained routing is a very important issue for printed circuit board (PCB) routing. Previous length-constrained routers all have assumptions on the routing topology, whereas practical designs may be free of any topological constraint. In this paper, we propose a routing scheme that deals with general topology. Unlike previous works, our approach does not impose any restriction on the routing topology. Moreover, our routing scheme is gridless. Its performance does not depend on the routing grid size of the input while the routers in the papers of Ozdal and Wong and Kubo et al. do. This is a big advantage because modern PCB routing configurations usually imply huge routing grids. The novelty of this work is that we view the length-constrained routing problem as an area assignment problem and use a placement structure, which is the bounded-sliceline grid, to help transform the area assignment problem into a mathematical programming problem.We then use an iterative approach to solve this mathematical programming problem. Experimental results show that our routing scheme can handle practical designs that previous routers cannot handle. For designs that they could handle, our router runs much faster. For example, in one of our data, we obtain the result in 88 s while the Lagrangian relaxation based router by Ozdal andWong takes more than one day.