The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Arbitrary convex and concave rectilinear block packing using sequence-pair
ISPD '99 Proceedings of the 1999 international symposium on Physical design
An enhanced perturbing algorithm for floorplan design using the O-tree representation
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Automatic datapath tile placement and routing
Proceedings of the conference on Design, automation and test in Europe
Revisiting floorplan representations
Proceedings of the 2001 international symposium on Physical design
Consistent floorplanning with super hierarchical constraints
Proceedings of the 2001 international symposium on Physical design
Rectilinear block packing using O-tree representation
Proceedings of the 2001 international symposium on Physical design
Device-level placement for analog layout: an opportunity for non-slicing topological representations
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Constrained polygon transformations for incremental floorplanning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Floorplan representations: Complexity and connections
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Constrained "Modern" Floorplanning
Proceedings of the 2003 international symposium on Physical design
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
An area-optimality study of floorplanning
Proceedings of the 2004 international symposium on Physical design
Abstraction and optimization of consistent floorplanning with pillar block constraints
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Fast evaluation of bounded slice-line grid
Journal of Computer Science and Technology
Signal-path driven partition and placement for analog circuit
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A fixed-die floorplanning algorithm using an analytical approach
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
An extended representation of Q-sequence for optimizing channel-adjacency and routing-cost
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Using red-black interval trees in device-level analog placement with symmetry constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Fast floorplanning by look-ahead enabled recursive bipartitioning
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A tree based novel representation for 3D-block packing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Discrete PSO for Multi-objective Optimization in VLSI Floorplanning
ISICA '09 Proceedings of the 4th International Symposium on Advances in Computation and Intelligence
BSG-route: a length-constrained routing scheme for general planar topology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hybrid algorithm for floorplanning using B*-tree representation
IITA'09 Proceedings of the 3rd international conference on Intelligent information technology application
Regularity-oriented analog placement with diffusion sharing and well island generation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
A quick generation method of sequence pair for block placement
ICCS'05 Proceedings of the 5th international conference on Computational Science - Volume Part III
An improved algorithm for sequence pair generation
ICCS'06 Proceedings of the 6th international conference on Computational Science - Volume Part I
LAYGEN II: automatic analog ICs layout generator based on a template approach
Proceedings of the 14th annual conference on Genetic and evolutionary computation
Practicality on placement given by optimality of packing
Proceedings of the 2013 ACM international symposium on International symposium on physical design
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A new method of packing the rectangles is proposed with applications to integrated circuit (IC) layout design. A special work-sheet, called the bounded-sliceline grid, is introduced. It consists of special segments that dissect the plane into rooms to which binary relations “right-of” and “above” are associated such that any two rooms are uniquely in either relation. A packing is obtained through an assignment of the modules into the rooms followed by a compaction procedure. Changing the assignments by swapping the contents of two rooms, a simulated annealing strategy is implemented to search for a good packing. Empirical results show that hundreds of rectangles are packed with a quite good quality in area efficiency. A wide adaptability is demonstrated specific to IC layout design. Ideas to handle a multilayer, nonrectangular chips with L-shaped modules are suggested