ACM Transactions on Design Automation of Electronic Systems (TODAES)
LEDA: a platform for combinatorial and geometric computing
LEDA: a platform for combinatorial and geometric computing
An enhanced perturbing algorithm for floorplan design using the O-tree representation
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Classical floorplanning harmful?
ISPD '00 Proceedings of the 2000 international symposium on Physical design
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Constrained polygon transformations for incremental floorplanning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Consistent placement of macro-blocks using floorplanning and standard-cell placement
Proceedings of the 2002 international symposium on Physical design
Floorplanning with alignment and performance constraints
Proceedings of the 39th annual Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Introduction to Algorithms
Corner block list: an effective and efficient topological representation of non-slicing floorplan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
DAC '82 Proceedings of the 19th Design Automation Conference
Fixed-Outline Floorplanning through Better Local Search
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Module packing based on the BSG-structure and IC layout applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fixed-outline floorplanning using robust evolutionary search
Engineering Applications of Artificial Intelligence
UFO: unified convex optimization algorithms for fixed-outline floorplanning
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents algorithms for a constrained version of the "modern" floorplanning problem proposed by Kahng in "Classical Floorplanning Harmful?" [1]. Specically, the constrained modern floorplanning problem (CMFP) is suitable when die-size is fixed, modules are permitted to have rectilinear shapes, and, in addition, the approximate relative positions of the modules are known. This formulation is particularly useful in two scenarios: (1) assisting an expert floorplan architect in a semi-automated floorplan methodology and (2) in incremental floorplanning. CMFP is shown to be NP hard. An algorithm based on a max-flow network formulation quickly identifies input constraints that are impossible to meet, thus permitting the floorplan architect to modify these constraints. Three algorithms (BFS, IBFS, CBFS) based on using BFS numbers to assign costs in a min-cost max-flow network formulation are presented. Experiments on standard benchmarks demonstrate that BFS and IBFS are fast and obtain zero whitespace floorplans.