Fixed-outline floorplanning using robust evolutionary search

Authors:
De-Sheng Chen;Chang-Tzu Lin;Yi-Wen Wang;Ching-Hwa Cheng
Affiliations:
Department of Computer Science and Information Engineering, Feng-Chia University, Taiwan;Department of Computer Science and Information Engineering, Feng-Chia University, Taiwan;Department of Computer Science and Information Engineering, Feng-Chia University, Taiwan;Department of Electronic Engineering, Feng-Chia University, Taiwan
Venue:
Engineering Applications of Artificial Intelligence
Year:
2007

Citing 12
Cited 2

How good are slicing floorplans?

Integration, the VLSI Journal
A new algorithm for floorplan design

DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Outline for a Logical Theory of Adaptive Systems

Journal of the ACM (JACM)
Classical floorplanning harmful?

ISPD '00 Proceedings of the 2000 international symposium on Physical design
B*-Trees: a new representation for non-slicing floorplans

Proceedings of the 37th Annual Design Automation Conference
Fast evaluation of sequence pair in block placement by longest common subsequence computation

DATE '00 Proceedings of the conference on Design, automation and test in Europe
FAST-SP: a fast algorithm for block placement based on sequence pair

Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Corner block list: an effective and efficient topological representation of non-slicing floorplan

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Constrained "Modern" Floorplanning

Proceedings of the 2003 international symposium on Physical design
Fixed-outline floorplanning: enabling hierarchical design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
VLSI module placement based on rectangle-packing by the sequence-pair

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Hierarchical congregated ant system for bottom-up VLSI placements

Engineering Applications of Artificial Intelligence
Variable-Order Ant System for VLSI multiobjective floorplanning

Applied Soft Computing

Quantified Score

Hi-index	0.00

Visualization

Abstract

Typical floorplanning concerns a series of objectives, such as area, wirelength, and routability, etc., with various aspect ratios of modules in a free-outline regime. However, in a hierarchical design flow for very large ASICs and SoCs, a floorplan can be completely useless for a situation where its outline is dissatisfied. In this paper, we study the fixed-outline floorplanning problem that is more applicable to the hierarchical design style. We develop an efficient algorithm based on robust evolutionary search and achieve substantially improved success rate. We also propose a new approach to handle soft modules to further adjust the generated floorplan to fit into the prescribed chip outline. The effectiveness of our methods is demonstrated on several large cases of MCNC and GSRC benchmarks.