Deterministic Built-in Pattern Generation for Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Sequential Circuit Test Generation Using a Symbolic/Genetic Hybrid Approach
Journal of Electronic Testing: Theory and Applications
Multi-objective design space exploration using genetic algorithms
Proceedings of the tenth international symposium on Hardware/software codesign
Combining Symbolic and Genetic Techniques for Efficient Sequential Circuit Test Generation
ETW '00 Proceedings of the IEEE European Test Workshop
An Application of Genetic Algorithms and BDDs to Functional Testing
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Genetic algorithms: the philosopher's stone or an effective solution for high-level TPG?
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
Efficient design space exploration for application specific systems-on-a-chip
Journal of Systems Architecture: the EUROMICRO Journal
Fixed-outline floorplanning using robust evolutionary search
Engineering Applications of Artificial Intelligence
RUBASTEM: a method for testing VHDL behavioral models
HASE'04 Proceedings of the Eighth IEEE international conference on High assurance systems engineering
Journal of Electronic Testing: Theory and Applications
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This paper discusses a new approach for generating test vectors, using test cultivation, for both combinational and sequential VLSI circuits described hierarchically at the transistor, gate, and higher levels. The approach is based on continuous mutation of a given input sequence and on analyzing the mutated vectors for selecting the test set. The hierarchical technique used in the analysis drastically reduces the memory requirements, allowing test generation for large circuits. The test cultivation algorithms are simulation-based and a test set can be cultivated for any circuit that can be simulated logically. In particular, general MOS digital designs can be handled, and both stuck-at and transistor faults can be accurately modeled. Using the approach, tests were generated with very high fault coverage for gate-level circuits as well as for transistor level circuits