High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Combining deterministic and genetic approaches for sequential circuit test generation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An effective test generation system for sequential circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Alternating Strategies for Sequential Circuit ATPG
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Sequential Circuit Test Generation Using Dynamic State Traversal
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A new approach for initialization sequences computation for synchronous sequential circuits
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Automatic VHDL Restructuring for RTL Synthesis Optimization and Testability Improvement
ICCD '98 Proceedings of the International Conference on Computer Design
Enhancing Topological ATPG with High-Level Information and Symbolic Techniques
ICCD '98 Proceedings of the International Conference on Computer Design
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A genetic algorithm framework for test generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Application of genetically engineered finite-state-machine sequences to sequential circuit ATPG
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Symbolic optimization of interacting controllers based on redundancy identification and removal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-cost sequential ATPG with clock-control DFT
Proceedings of the 39th annual Design Automation Conference
An EFSM-based approach for functional ATPG
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Genetic algorithms: the philosopher's stone or an effective solution for high-level TPG?
HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
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Symbolic and genetic techniques are combined in a new approach to sequential circuit test generation that uses circuit decomposition, rather than the algorithmic decomposition used in previous hybrid test generators. Symbolic techniques are used to generate test sequences for the control logic, and genetic algorithms are used to generate sequences for the datapath. The combined sequences provide higher fault coverages than those generated by existing deterministic and GA-based test generators, and execution times are significantly lower in many cases.