Hierarchical multi-level fault simulation of large systems
Journal of Electronic Testing: Theory and Applications
Sequential test generation at the register-transfer and logic levels
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Adaptation in natural and artificial systems
Adaptation in natural and artificial systems
Sequential circuit test generation in a genetic algorithm framework
DAC '94 Proceedings of the 31st annual Design Automation Conference
Split circuit model for test generation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
CRIS: a test cultivation program for sequential VLSI circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Unified Methods for VLSI Simulation and Test Generation
Unified Methods for VLSI Simulation and Test Generation
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
A Test Generation Method for Sequential Circuits Based on Maximum Utilization of Internal States
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Sequential Test Generation Based on Real-Value Logic
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Combining deterministic and genetic approaches for sequential circuit test generation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Gate-level test generation for sequential circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Distributed Test Pattern Generation for Stuck-At Faults in Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Testing DSP cores based on self-test programs
Proceedings of the conference on Design, automation and test in Europe
Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Deterministic test pattern generation techniques for sequential circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Simulation based test generation for scan designs
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Sequential Circuit Test Generation Using a Symbolic/Genetic Hybrid Approach
Journal of Electronic Testing: Theory and Applications
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Alternating Strategies for Sequential Circuit ATPG
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Sequential Circuit Test Generation Using Dynamic State Traversal
EDTC '97 Proceedings of the 1997 European conference on Design and Test
On improving genetic optimization based test generation
EDTC '97 Proceedings of the 1997 European conference on Design and Test
MOSAIC: A Multiple-Strategy Oriented Sequential ATPG for Integrated Circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Combining Symbolic and Genetic Techniques for Efficient Sequential Circuit Test Generation
ETW '00 Proceedings of the IEEE European Test Workshop
Fast Algorithms for Computer IDDQ Tests for Combination Circuits
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
An Application of Genetic Algorithms and BDDs to Functional Testing
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
TOV: sequential test generation by ordering of test vectors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
Simulation-based test vector generators require much less computer time than deterministic ATPG but they generate longer test sequences and sometimes achieve lower fault coverage. This is due to the divergence in the search process. In this paper, we propose a correction technique for simulation-based ATPG. This technique is based on identifying the diverging state and on computing a fault cluster (faults close to each other). A set of candidate faults from the cluster is targeted with a deterministic ATPG and the resulting test sequence is used to restart the search process of the simulation-based technique. This above process is repeated until all faults are detected or proven to be redundant/untestable. The program implementing this approach has been used to generate tests with very high fault coverage, and runs about 10 times faster than traditional deterministic techniques with very good test quality in terms of test length and fault coverage.