Adaptation in natural and artificial systems
Adaptation in natural and artificial systems
Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Sequential circuit test generation in a genetic algorithm framework
DAC '94 Proceedings of the 31st annual Design Automation Conference
Combining deterministic and genetic approaches for sequential circuit test generation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
CRIS: a test cultivation program for sequential VLSI circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
An Experimental Chip to Evaluate Test Techniques: Chip and Experiment Design
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
An Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic Algorithms
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Advanced Techniques for GA-based sequential ATPGs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
On the effects of test compaction on defect coverage
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Enhanced genetic algorithms in constrained search spaces with emphasis in parallel environments
Enhanced genetic algorithms in constrained search spaces with emphasis in parallel environments
Simulation based test generation for scan designs
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
On test generation by input cube avoidance
Proceedings of the conference on Design, automation and test in Europe
Dynamic test compaction for a random test generation procedure with input cube avoidance
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Random test generation with input cube avoidance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
A Abstract: Test generation procedures based on genetic optimization were shown to be effective in achieving high fault coverage for benchmark circuits. In a genetic optimization procedure, the crossover operator accepts two test patterns t/sub 1/ and t/sub 2/, and randomly copies parts of t/sub 1/ and parts of t/sub 2/ into one or more new test patterns. Such a procedure does not take advantage of circuit properties that may aid in generating more effective test patterns. In this work, we propose a representation of test patterns where subsets of inputs are considered as indivisible entities. Using this representation, crossover copies all the values of each subset either from t/sub 1/ or from t/sub 2/. By keeping input subsets undivided, activation and propagation capabilities of t/sub 1/ and t/sub 2/ are captured and carried over to the new test patterns. The effectiveness of this scheme is demonstrated by experimental results.