CRIS: a test cultivation program for sequential VLSI circuits
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Sequential circuit test generation in a genetic algorithm framework
DAC '94 Proceedings of the 31st annual Design Automation Conference
Contest: a concurrent test generator for sequential circuits
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
An Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic Algorithms
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Gate-level test generation for sequential circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SAARA: a simulated annealing algorithm for test pattern generation for digital circuits
SAC '97 Proceedings of the 1997 ACM symposium on Applied computing
Hybrid Fault Simulation for Synchronous Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Dynamic state traversal for sequential circuit test generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits
Journal of Electronic Testing: Theory and Applications
Simulation based test generation for scan designs
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Evolutionary Techniques for Minimizing Test Signals Application Time
Proceedings of the Applications of Evolutionary Computing on EvoWorkshops 2002: EvoCOP, EvoIASP, EvoSTIM/EvoPLAN
SETN '02 Proceedings of the Second Hellenic Conference on AI: Methods and Applications of Artificial Intelligence
On improving genetic optimization based test generation
EDTC '97 Proceedings of the 1997 European conference on Design and Test
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
DNA and quantum based algorithms for VLSI circuits testing
Natural Computing: an international journal
DNA computing approach for automated test pattern generation for digital circuits
International Journal of Systems Science
TOV: sequential test generation by ordering of test vectors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Genetic Algorithms have been recently investigated as an efficient approach to test generation for synchronous sequential circuits. In this paper we propose a set of techniques which significantly improves the performance of a previously proposed the GA-based ATPG algorithm: in particular, the new techniques enhance the capability of the algorithm in terms of test length minimization and fault excitation. We report some experimental results gathered with a prototypical tool and show that a well-tuned GA-based ATPG is generally superior to both symbolic and topological ones in terms of achieved Fault Coverage and required CPU time.