CRIS: a test cultivation program for sequential VLSI circuits
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Sequential circuit test generation in a genetic algorithm framework
DAC '94 Proceedings of the 31st annual Design Automation Conference
Combining deterministic and genetic approaches for sequential circuit test generation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On generating compact test sequences for synchronous sequential circuits
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
On static compaction of test sequences for synchronous sequential circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
An effective test generation system for sequential circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Techniques for improving the efficiency of sequential circuit test generation
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
IDDQ and AC Scan: The War Against Unmodelled Defects
Proceedings of the IEEE International Test Conference on Test and Design Validity
An Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic Algorithms
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Too much delay fault coverage is a bad thing
Proceedings of the IEEE International Test Conference 2001
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Advanced Techniques for GA-based sequential ATPGs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Sequential Circuit Test Generation Using Dynamic State Traversal
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Simulator-oriented fault test generator
DAC '77 Proceedings of the 14th Design Automation Conference
Vector restoration based static compaction of test sequences for synchronous sequential circuits
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
LOCSTEP: A Logic Simulation-Based Test Generation Procedure
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
PROPTEST: a property-based test generator for synchronous sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.03 |
We describe a new approach to test generation for stuck-at faults in synchronous sequential circuits. Under this approach, the input vectors comprising the test sequence are fixed in advance. The process of generating the test sequence consists of ordering the precomputed input vectors such that the resulting test sequence has as high a fault coverage as possible. The advantage of this approach is that its computational complexity is limited by limiting the search space to a given set of input vectors and a given test sequence length. We describe a specific implementation of this approach. Experimental results demonstrate that restricting the search space to a fixed number of precomputed input vectors is sufficient for achieving the highest known fault coverage, or a fault coverage close to it, for benchmark circuits.