Digital logic testing and simulation
Digital logic testing and simulation
Proofs: a fast, memory efficient sequential circuit fault simulator
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
On test set preservation of retimed circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Gate-level test generation for sequential circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Partial scan design based on circuit state information
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Synthesis of Sequential Circuits by Redundancy Removal and Retiming
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Illegal state space identification for sequential circuit test generation
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Test generation for Gigahertz processors using an automatic functional constraint extractor
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Dynamic state traversal for sequential circuit test generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Deterministic test pattern generation techniques for sequential circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Testability Implications of Performance-Driven Logic Synthesis
IEEE Design & Test
A comprehensive approach to the partial scan problem using implicit state enumeration
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test configurations to enhance the testability of sequential circuits
ATS '95 Proceedings of the 4th Asian Test Symposium
Software transformations for sequential test generation
ATS '95 Proceedings of the 4th Asian Test Symposium
Alternating Strategies for Sequential Circuit ATPG
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Surprises in Sequential Redundancy Identification
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Sequential Circuit Test Generation Using Dynamic State Traversal
EDTC '97 Proceedings of the 1997 European conference on Design and Test
15.3 Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
At-Speed Logic BIST Using a Frozen Clock Testing Strategy
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Partial Scan Design Based on Circuit State Information and Functional Analysis
IEEE Transactions on Computers
TOV: sequential test generation by ordering of test vectors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast enhancement of validation test sets for improving the stuck-at fault coverage of RTL circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The research reported in this paper was conducted to identify those attributes, of both sequential circuits and structural, sequential automatic test pattern generation (ATPG) algorithms, which can lead to extremely high test generation times. The retiming transformation is used as a mechanism to create two classes of circuits which present varying degrees of complexity for test generation. It was observed for three different sequential test generators that the increase in complexity of testing is not due to those circuit attributes (namely sequential depth and cycles) which have traditionally been associated with such complexity. Evidence is instead provided that another circuit attribute, termed density of encoding, is a key indicator of the complexity of structural, sequential ATPG.