Redundancies and don't cares in sequential logic synthesis
Journal of Electronic Testing: Theory and Applications
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DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
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On redundancy and untestability in sequential circuits
On redundancy and untestability in sequential circuits
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IEEE Transactions on Computers
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Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
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Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
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This paper addresses some misconceptions about redundancy in synchronous sequential circuits. We provide examples to illustrate the differences between untestability and redundancy and discuss existing techniques to identify sequential redundancy. We show that some of these methods are based on incorrect theoretical results. Specifically, we show that untestable faults in balanced pipeline circuits are not necessarily redundant, and that a constant function (i.e. a signal that is always 0 or 1 after initialization) does not always indicate a redundancy. We also show that adding a global reset mechanism or retiming synchronous circuitry may introduce redundancies.