Sequential logic optimization by redundancy addition and removal

  • Authors:
  • Luis Entrena;Kwang-Ting Cheng

  • Affiliations:
  • Universidad Politecnica de Madrid, ETSII-DIE, Jose Gutierrez Abascal, 228006 Madrid, Spain;AT&T Bell Laboratories, Murray Hill, NJ

  • Venue:
  • ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
  • Year:
  • 1993

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Abstract