Layout driven logic synthesis for FPGAs
DAC '94 Proceedings of the 31st annual Design Automation Conference
Circuit partitioning with logic perturbation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Timing optimization by an improved redundancy addition and removal technique
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Sequential logic optimization by redundancy addition and removal
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Circuit Optimization by Rewiring
IEEE Transactions on Computers
IBAW: an implication-tree based alternative-wiring logic transformation algorithm
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Perturb and simplify: multilevel Boolean network optimizer
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Postlayout logic restructuring using alternative wires
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combinational and sequential logic optimization by redundancy addition and removal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Identifying Redundant Wire Replacements for Synthesis and Verification
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
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In this paper, we present a competent algorithm to the alternative wiring problem by exploring the relationship between dominators of a target wire. Alternative wiring refers to the process of adding a redundant connection to a circuit such that a target connection will become redundant and can be removed from the circuit. The well-known ATPG-based alternative wiring scheme. Redundancy Addition and Removal for Multi-level Boolean Optimization (RAMBO), has shown its effectiveness in solving the problem in the last decade. The deficiency of RAMBO lies in its long execution time for redundancy identification among a large set of candidate alternative wires in the circuit. Implication-tree Based Alternative Wiring Logic Transformation Algorithm (IBAW) improves the speed of RAMBO by introducing an implication-tree structure for source node identification. Our approach of investigating the dominator relationship suggest that a large subset of unnecessary redundancy checks can be further avoided in order to improve the efficiency. Experiments were performed on MCNC benchmark circuits and results are compared to those of RAMBO and IBAW. Results show that our proposed algorithm improves IBAW with a 2.3 times speedup. Moreover, our implementation runs 8.8 times faster than RAMBO while solution quality is still maintained.