Multi-level logic optimization by implication analysis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Circuit partitioning with logic perturbation
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Fast Boolean optimization by rewiring
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Post-layout logic restructuring for performance optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
Single-pass redundancy addition and removal
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Perturb and simplify: multilevel Boolean network optimizer
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Postlayout logic restructuring using alternative wires
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LOT: Logic Optimization with Testability. New transformations for logic synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combinational and sequential logic optimization by redundancy addition and removal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improved alternative wiring scheme applying dominator relationship
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
False-noise analysis using logic implications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
False-noise analysis using logic implications
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
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