Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Post-layout logic restructuring for performance optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
Logic transformation for low power synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Circuit Optimization by Rewiring
IEEE Transactions on Computers
Domino logic synthesis minimizing crosstalk
Proceedings of the 37th Annual Design Automation Conference
Implication graph based domino logic synthesis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Logic Design Validation via Simulation and Automatic Test Pattern Generation
Journal of Electronic Testing: Theory and Applications
Further improve circuit partitioning using GBAW logic perturbation techniques
Proceedings of the conference on Design, automation and test in Europe
Generalized reasoning scheme for redundancy addition and removal logic optimization
Proceedings of the conference on Design, automation and test in Europe
IBAW: an implication-tree based alternative-wiring logic transformation algorithm
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Circuit partitioning with coupled logic restructuring techniques
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Functional extension of structural logic optimization techniques
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Improved alternative wiring scheme applying dominator relationship
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Logic transformation for low-power synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Wire reconnections based on implication flow graph
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Single-pass redundancy addition and removal
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
BETSY: synthesizing circuits for a specified BIST environment
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A new enhanced SPFD rewiring algorithm
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
ATPG-based logic synthesis: an overview
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Further improve circuit partitioning using GBAW logic perturbation techniques
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
SPFD-based effective one-to-many rewiring (OMR) for delay reduction of LUT-based FPGA circuits
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Implicit enumeration of structural changes in circuit optimization
Proceedings of the 41st annual Design Automation Conference
An Improved Approach for AlternativeWires Identi.cation
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Multiple wire reconnections based on implication flow graph
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Soft error rate reduction using redundancy addition and removal
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
SAT-controlled redundancy addition and removal: a novel circuit restructuring technique
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
ECR: a low complexity generalized error cancellation rewiring scheme
Proceedings of the 47th Design Automation Conference
Rewiring using IRredundancy removal and addition
Proceedings of the Conference on Design, Automation and Test in Europe
Improvements on efficiency and efficacy of SPFD-based rewiring for LUT-based circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On rewiring and simplification for canonicity in threshold logic circuits
Proceedings of the International Conference on Computer-Aided Design
ECR: A Powerful and Low-Complexity Error Cancellation Rewiring Scheme
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A low-cost, systematic methodology for soft error robustness of logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we present logic optimization techniques for multilevel combinational networks. Our techniques apply a sequence of perturbations which result in simplification of the circuit. The perturbation and simplification is achieved through wires/gates addition and removal which are guided by the Automatic Test Pattern Generation (ATPG) based reasoning. The main operations of our approaches are incremental transformations of the circuit (such as adding wires/gates and changing gate's functionality) to remove some particular wire, At each iteration, a summary information of such wires/gates addition and removal is precomputed first. Then, a transformation is chosen to remove several wires at once. We have performed experiments on MCNC benchmarks and compared the results to those of misII and RAMBO. Experimental results are very encouraging