Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
A topological search algorithm for ATPG
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Logic synthesis for engineering change
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
An efficient algorithm for local don't care sets calculation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
FIRE: a fault-independent combinational redundancy identification algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing optimization by an improved redundancy addition and removal technique
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Gate-level synthesis for low-power using new transformations
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Post-layout logic restructuring for performance optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
LIBRA—a library-independent framework for post-layout performance optimization
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Power reduction and power-delay trade-offs using logic transformations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Circuit Optimization by Rewiring
IEEE Transactions on Computers
A Computing Procedure for Quantification Theory
Journal of the ACM (JACM)
Fast post-placement rewiring using easily detectable functional symmetries
Proceedings of the 37th Annual Design Automation Conference
On removing multiple redundancies in combinational circuits
Proceedings of the conference on Design, automation and test in Europe
Single-pass redundancy addition and removal
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Perturb and simplify: multilevel Boolean network optimizer
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Logic optimization and equivalence checking by implication analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LOT: Logic Optimization with Testability. New transformations for logic synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient Boolean division and substitution using redundancy addition and removing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance optimization by interacting netlist transformations and placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SPFD: A new method to express functional flexibility
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combinational and sequential logic optimization by redundancy addition and removal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SAT-based ATPG using multilevel compatible don't-cares
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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The ultimate goal of logic synthesis is to explore implementation flexibility toward meeting design targets, such as area, power, and delay. Traditionally, such flexibility is expressed using "don't cares" and we seek the best implementation that does not violate them. However, the calculation and storing of don't care information is CPU and memory-intensive. In this paper, we give an overview of logic synthesis approaches based on techniques developed for Automatic Test Pattern Generation (ATPG). Instead of calculating and storing don't cares explicitly, ATPG-based logic synthesis techniques calculate the flexibility implicitly. Low CPU and memory usage make those techniques applicable for practical industrial circuits. Also, the basic ATPG-based logic level operations create predictable, small layout perturbations, making an ideal foundation for efficient physical synthesis. Theoretical results show that an efficient, yet simple add-a-wire-and-remove-a-wire operation covers all possible complex logic transformations.