On removing multiple redundancies in combinational circuits

Authors:
S.-C. Chang;D. I. Cheng;C.-W. Yeh
Affiliations:
National Chung Cheng Univ., Chia-Yi, Taiwan, R.O.C.;Exemplar Logic Inc., San Jose, CA;National Chung Cheng Univ., Chia-Yi, Taiwan, R.O.C.
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
1998

Citing 3
Cited 3

Multi-level logic optimization by implication analysis

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Fast Boolean optimization by rewiring

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Sequential logic optimization by redundancy addition and removal

ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design

ATPG-based logic synthesis: an overview

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A Minimum Cut Based Re-Synthesis Approach

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Finding Multiple Equivalence-Preserving Transformations in Combinational Circuits through Incremental-SAT

Journal of Electronic Testing: Theory and Applications

Quantified Score

Hi-index	0.00

Visualization

Abstract

Redundancy removal is an important step in combinational logic optimization. After a redundant wire is removed, other originally redundant wires may become irredundant, and some originally irredundant wires may become redundant. When multiple redundancies exist in a circuit, this creates a problem where we need to decide which redundancy to remove first. In this paper, we present an analysis and a very efficient heuristic to deal with multiple redundancies. We associate with each redundant wire a Boolean function that describes how the wire can remain redundant after removing other wires. When multiple redundancies exist, this set of Boolean functions characterizes the global relationship among redundancies.