Timing optimization by an improved redundancy addition and removal technique
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
On removing multiple redundancies in combinational circuits
Proceedings of the conference on Design, automation and test in Europe
Logic synthesis through local transformations
IBM Journal of Research and Development
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Combinational and sequential logic optimization by redundancy addition and removal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A new re-synthesis approach that benefits from min-cut based partitioning is proposed. This divide and conquer approach is shown to improve the performance of existing synthesis tools on a variety of benchmarks.