An ALGOL-like computer design language
Communications of the ACM
Logic Design of Digital Systems
Logic Design of Digital Systems
Digital Systems: Hardware Organization and Design
Digital Systems: Hardware Organization and Design
DAC '81 Proceedings of the 18th Design Automation Conference
Register-transfer level digital design automation: The allocation process
DAC '78 Proceedings of the 15th Design Automation Conference
LORES - Logic Reorganization System
DAC '78 Proceedings of the 15th Design Automation Conference
DAC '80 Proceedings of the 17th Design Automation Conference
Development and application of a designer oriented cyclic simulator
DAC '76 Proceedings of the 13th Design Automation Conference
Quality of designs from an automatic logic generator (ALERT)
DAC '70 Proceedings of the 7th Design Automation Workshop
The CMU design automation system: An example of automated data path design
DAC '79 Proceedings of the 16th Design Automation Conference
The description, simulation, and automatic implementation of digital computer processors
The description, simulation, and automatic implementation of digital computer processors
Automated exploration of the design space for register-transfer (rt) systems.
Automated exploration of the design space for register-transfer (rt) systems.
Translation of a DDL Digital System Specification to Boolean Equations
IEEE Transactions on Computers
Methods Used in an Automatic Logic Design Generator (ALERT)
IEEE Transactions on Computers
Transformation-Based Verification Using Generalized Retiming
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Polaris: Polarity propagation algorithm for combinational logic synthesis
DAC '84 Proceedings of the 21st Design Automation Conference
A new switching-level approach to multiple-output functions synthesis
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
A Minimum Cut Based Re-Synthesis Approach
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Global Flow Analysis in Automatic Logic Design
IEEE Transactions on Computers
Redundancy and Don't Cares in Logic Synthesis
IEEE Transactions on Computers
An Inductive Assertion Method for Register Transfer Level Design Verification
IEEE Transactions on Computers
Optimal logic synthesis and testability: two faces of the same coin
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
ABC: an academic industrial-strength verification tool
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
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A logic designer today faces a growing number of design requirements and technology restrictions, brought about by increases in circuit density and processor complexity. At the same time, the cost of engineering changes has made the correctness of chip implementations more important, and minimization of circuit count less so. These factors underscore the need for increased automation of logic design. This paper describes an experimental system for synthesizing synchronous combinational logic. It allows a designer to start with a naive implementation produced automatically from a functional specification, evaluate it with respect to these many factors and incrementally improve this implementation by applying local transformations until it is acceptable for manufacture. The use of simple local transformations in this system ensures correct implementations, isolates technology-specific data, and will allow the total process to be applied to larger, VLSI designs. The system has been used to synthesize masterslice chip implementations from functional specifications, and to remap implemented masterslice chips from one technology to another while preserving their functional behavior.