Computer Logic, Testing and Verification
Computer Logic, Testing and Verification
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
MINI: a heuristic approach for logic minimization
IBM Journal of Research and Development
Logic synthesis through local transformations
IBM Journal of Research and Development
Design methodology for the S/390 parallel enterprise server G4 microprocessors
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Global Flow Analysis in Automatic Logic Design
IEEE Transactions on Computers
WoLFram- A Word Level Framework for Formal Verification
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
LSS: a system for production logic synthesis
IBM Journal of Research and Development
Optimal logic synthesis and testability: two faces of the same coin
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Automatic test pattern generation
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
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A signal in a logical network is called redundant if it can be replaced by a constant without changing the function of the network. Detecting redundancy is important for two reasons: guaranteeing coverage in stuck-fault testing, and simplifying multilevel logic without converting to two levels. In particular, removing redundancy allows simplification in the presence of don't cares. The algorithm for redundancy removal described in this paper has been used successfully for both of the above purposes. It achieves savings in computer resources at the expense of possibly failing to discover some redundancies.