Optimal logic synthesis and testability: two faces of the same coin

• Authors: Srinivas Devadas;Hi-Keung Tony Ma;A. Richard Newton;Alberto Sangiovanni-Vincentelli
• Venue: ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
• Year: 1988

Logic synthesis has been the subject of many years of research in both academic and industrial laboratories. The algorithms developed in these arenas have matured sufficiently to be practical for real circuit designs and are rapidly gaining acceptance in the design of complex digital products. The use of such synthesis tools increases the need for automatic test generation tools since the logic produced by the synthesis program has little or no meaning to the designer. While a substantial body of work also exists in the testing area, for both combinational and sequential circuits, test generation for sequential machines has remained a post-design process in almost all cases. Design-for-test techniques, such as scan-based methods, have been developed to facilitate post-design test generation by reducing the sequential test problem to one of testing commbinational circuits, for which a number of efficient techniques have been developed. It is the premise of this paper that there is a very strong relationship between a successful (optimal) logic synthesis strategy and a fully testable circuit - for both combinational and sequential designs. Today, combinational logic synthesis algorithm are known which can ensure irredundant. and fully testable designs for both two-level (e.g. PLA) and multi-level implementations. These procedures also produce test vectors which will detect all single stuck-at faults as a by-product of the minimization step. We believe a similar, synthesis-orientetd approach to the testing of sequential machnies is practical. Using such an approach, it would be possible for the sequential synthesis system to guarantee that the generated machine is fully testable without resorting to a full scan approach and the use of additional test points (e.g. partial scan) would only be needed to compact the test scquence. Following a, brief review of the state-of-the-art in combinational and seqnential logic synthesis, algorithnis which can eusure irredundant and fully testable combinational and scquential circuits are reviewed. Directions for future research involving the antomatic synthesis of both fully and easily testable combinational and sequential circuits are also indicated.