A testing strategy for PLAs

  • Authors:
  • Charles W. Cha

  • Affiliations:
  • -

  • Venue:
  • DAC '78 Proceedings of the 15th Design Automation Conference
  • Year:
  • 1978

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Abstract

Programmable Logic Arrays (PLA) are finding increasing use as a cost-effective means to utilize LSI electronics. In this paper, three classes of faults, namely stuck faults, shorts and cross-point defects are defined and characterized in a PLA. The relationship between the test sets and their faults among all three classes are discussed. Finally, an algorithm for generating a test set for all three classes of faults is presented.