Optimal order of the VLSI IC testing sequence

Authors:
Wojciech Maly
Affiliations:
Department of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, Pennsylvania
Venue:
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Year:
1986

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Abstract

In this paper we introduce a technique which manipulates the order of tests to minimize the length of the testing sequence. Probabilities of fault occurrences which are analyzed in terms of random phenomena inherent in VLSI manufacturing process are used to determine this optimal testing order. Simulation of the PLA testing process indicates that there exist possibilities for the significant improvement in testing efficiency of the actual VLSI circuit.